AI Compiler Engineer

Grow with us AI Compiler Engineer — Research Team Austin, Texas This is not a remote work opportunity. MLIR Architecture | Compiler Infrastructure | 5G/6G Silicon | Bare-Metal AI The Mission Most AI compiler engineers optimize models for GPUs that already exist. You're going to optimize them for silicon that doesn't yet. As our Senior AI Compiler Engineer, you're not porting a framework, tweaking a runtime, or wrapping CUDA libraries. You're doing something far rarer and far harder — building a complete MLIR-based compiler stack from the ground up, purpose-built to run massive AI models like Llama 3 on bare-metal 5G/6G telecommunications silicon, where there's no OS to bail you out and every byte of memory is accounted for. The gap between a research model and hardware-optimized silicon execution is one of the most technically brutal problems in the industry right now. You'll be the engineer who closes it. What You'll Actually Be Doing MLIR Architecture — Own the Stack You'll design and implement custom MLIR dialects from scratch — TableGen definitions, transformation passes, and the dialect conversion infrastructure that bridges the world of high-level AI graphs and the cold, hard reality of custom silicon. This is greenfield compiler work at its most consequential. Lowering & Legalization — Zero Tolerance for Approximation Take high-level computational graphs exported from JAX and StableHLO and lower them, step by step, into hardware-specific IR without losing a single bit of mathematical fidelity. Every op must legalize. Every semantic must survive the descent. Concurrency & Memory Modeling — Orchestrate the Machine There's no virtual memory here. No garbage collector. No safety net. You'll build static scheduling and tiling passes that choreograph data movement between HBM and on-chip local memory with surgical precision — because on this hardware, getting it wrong isn't a performance regression, it's a failure. Production C++ — Code That Ships to Silicon You'll