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$ cat jobs/physical-design-engineer-block-level-subsystem-implementatio-etched-a5b423515d72.json

Physical Design Engineer - Block Level, Subsystem Implementation

Etched·Worldwide·San Jose·mid
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About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market. Key Responsibilities - Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII. - Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation. - Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna). - Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level. - Collaborate with RTL Designers and provide Physical Design feedback to improve PPA. - Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow. - Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks. You may be a good fit if you have - 5-10+ years of previous experience with PD - Tools, flow, and design methodology from RTL synthesis to GDSII sign-off - Experience with back-end design and timing closure on advanced process nodes