$ cat jobs/physical-design-engineer-flow-methodologies-etched-5e72c469c4d0.json
Physical Design Engineer - Flow & Methodologies
About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Methodology Engineer, you will architect our PD flow from first principles. You will own the infrastructure that allows our design team to iterate at unprecedented speeds, directly accelerating our time-to-market and enabling PPA gains that aren't possible with off-the-shelf CAD methodologies. Key Responsibilities - Architect, build, and maintain our automated RTL-to-GDSII flow, from synthesis through place and route to signoff handoff. - Automate PD flows end to end, including regression running, run management, and release and version control of flow configurations. - Build and own the CAD infrastructure supporting PD, including tool version qualification and deployment, and efficient use of compute and licenses. - Drive dashboards that show the convergence of projects related to PD, including timing, physical verification, and utilization trends. - Optimize tool flows and work with EDA vendors to evaluate and incorporate the latest features. - Define reference flows, QoR targets, and delivery checklists for 3rd party physical design services, and audit deliveries against them. - Partner with block and top-level owners to debug flow issues and encode fixes into the methodology rather than one-off patches. - Create block level and full chip level PG mesh from scratch using design rule documents, design requirements, and EM/IR feedback. - Create and maintain a DRC-clean floorplanning flow and enable floorplan signoff c