Physical Design Engineer

We are looking for a Physical Design Engineer to join our Analog Backend team and work on the digital island implementation within our analog chips. This role is ideal for someone who enjoys solving complex physical design challenges in mixed-signal environments. What You’ll Do Implement key aspects of the ASIC physical design flow, including floorplanning, placement optimization, clock tree synthesis, routing, and physical verification Optimize designs for performance, reliability, and manufacturability Perform chip-level power integrity analysis across multiple voltage domains (IR drop, signal EM, and power EM) Work on digital implementation embedded in analog environments Collaborate with global cross-functional teams including analog designers and verification engineers Experience in ASIC Physical Design Strong understanding of floorplanning, placement, CTS, routing, and sign-off checks Knowledge of power integrity analysis (IR drop and electromigration) A team player who enjoys working in an international, collaborative environment Analog Layout experience is a plus The expected annual pay range for this position is €39,000–€52,000. Please note that the final offer will depend on factors such as geographic location, relevant experience, and the candidate’s skill set. This role is also eligible for a bonus. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of li