Power Integrity Engineer

About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Power Integrity (PI) Engineer to join our platform electrical engineering team. In this role, you will own the power integrity methodology for high-power PCB and system designs — from early architecture through final release — ensuring robust power delivery to high-performance ASICs and supporting components across all operating conditions. Key Responsibilities - Perform pre- and post-layout PDN analysis for high-current ASIC power rails: target impedance profiling, decoupling capacitor selection and placement optimization, and plane resonance analysis. - Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers. - Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network. - Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance against ASIC power specifications. - Perform power-plane thermal co-simulation and work with mechanical teams on thermal-electrical tradeoffs for high-current delivery. - Drive design rule checks for PI compliance; work with layout teams in Cadence Allegro / Sigrity PowerDC/PowerSI or Ansys SIwave. - Collaborate with power design, PCB layout, and ASIC/package teams to define power delivery architecture and review guidelines early in the product lifecycle. - Support bring-up, debug rail-level issues (droop, ripple, transient excursions),