Principal Analog Design Engineer

Architect, design and verify CMOS analog blocks for custom ASICs to meet stringent performance, area, power and timeline constraints. Blocks include Tx, Rx, PLL and miscellaneous high-precision analog circuits. Responsibilities: DDR I/O Design: Develop and optimize high-speed DDR I/O interfaces, ensuring signal integrity, noise immunity, and compatibility with industry standards. Principal Liaison: Liaise between Analog Design Team and Verification/Validation/Test teams. Analyze Si ATE/Bench data against product spec. Use Excel/MATLAB/scripts to efficiently parse through large data set extracting actionable information. Collaboration: Work closely with digital design engineers, systems engineers, and other stakeholders to ensure seamless integration of analog and digital components. Technical Leadership: Provide technical guidance and mentorship to junior engineers and contribute to the development of best practices and design methodologies. Design Verification: Conduct comprehensive simulations and testing to validate design performance and reliability. Address any issues and implement corrective actions as needed. Documentation: Create detailed design documentation, including specifications, schematics, and design reports. Ensure that all design activities are well-documented and comply with internal and external standards. Innovation: Stay abreast of industry trends and emerging technologies. Propose and implement innovative solutions to enhance product performance and capabilities with focus on low power circuit design. Circuit Reliability: Ensure designs meet EM/IR/Aging requirements. Layout: Ensure layouts meet high analog standards for matching and performance. Advanced degree in Electronics/Microelectronics Engineering or related discipline. 10-15 years of analog circuit design experience. Expertise in high-speed DDR I/O interface design and optimization - emphasis on DDR5/DDR6 IO architecture, Client/Data Center Server circuits and system design, validation