Principal Electrical Engineer

Renesas is looking for an experienced Digital Design Engineer for our RadHard product team. This team develops high performance, radiation-hardened mixed-signal integrated solutions. The environment is fast paced and team members are empowered to make decisions within the scope of their job function. The successful candidate will be responsible for designingdigital circuits and supporting the mixed-signal verification environment. • Actively involved in all stages of product development including specification, design, synthesis, verification, timing analysis, design for test and silicon debug. • Architecting and writing the RTL for such circuits as digital interfaces, controllers, state machines and algorithms. • Performing synthesis and achieving timing convergence. • Develop and verify self-tested test benches for Mixed-signal chips and sub-circuits. • Strives for maximal verification coverage in the most time efficient manner. • Works with team to integrate the AMS and DV verification plans into one Master verification plan. • Works diligently to accomplish project goals and meet schedule requirements. • Drives towards continuous personal, team, project and Company improvement Required: 10+ years' experience in Verilog RTL coding and versed in VerilogAMS, VerilogA, Verilog (or SV) languages for both ASICs and FPGAs MSEE/PhD with relevant work experience with a strong background in digital design Proficient developing design constraints and Synthesis scripts. Experience with behavioral top level modeling and mixed signal verification methodology. Experience with scan insertion and ATPG generation. Must be able to work independently with limited supervision. Must be very organized, self-motivated and passionate about the work. Language skills: Written and verbal English language proficiency required. Tools: Cadence Design Tools and Synopsys DC proficiency required. Cadence AMS design flow experience is a definite plus. Preferred: PhD in EE 15+ years' experience Di