$ cat jobs/principal-engineer-rtl-design-renesaselectronics-f632c133e0ec.json
Principal Engineer, RTL Design
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. SoC Architecture & Integration Lead integration of complex multi-billion transistor SoCs comprising CPUs, GPUs, NPUs, AI accelerators, memory subsystems, and high-speed peripherals. Define and implement scalable SoC architectures, subsystem partitioning, and integration strategies. Drive top-level RTL integration, IP assembly, and system-level design closure. Collaborate with architecture, verification, physical design, DFT, firmware, and software teams throughout the development lifecycle. NoC & Interconnect Architecture Architect and integrate advanced Network-on-Chip (NoC) solutions for high-bandwidth and low-latency data movement. Optimize traffic flows, QoS, coherency, memory access, and interconnect performance. Define clocking, reset, and power strategies across complex interconnect f