Principal Package Design Engineer

At Renesas, we are more than just a semiconductor company; we are the engine behind a "safer, smarter, and more sustainable" future. Headquartered locally in the heart of San Jose, our Silicon Valley team is at the forefront of innovation in Automotive, Industrial, Infrastructure, and IoT technologies. By blending cutting-edge embedded processing with world-class analog and power expertise, we develop "Winning Combinations" that power billions of intelligent devices globally. Joining our San Jose office means joining a collaborative, forward-thinking environment where your work directly impacts the next generation of AI-driven infrastructure and green energy solutions. Principal Package Design Engineer Location: Hybrid at main Renesas Electronics America locations (San Jose, CA / Austin, TX) Department: Semiconductor Power Product Group Reports To: Senior Principal, Device Design Packaging Technology, Strategy, Operations Position Summary We are seeking a Principal Package Design Engineer to lead the development and integration of next-generation packaging solutions for high-performance semiconductors and electronic products. This role will focus on advanced package architecture, assembly processes, thermal and mechanical reliability, and cross-functional collaboration with design, applications, product engineering, manufacturing, suppliers, and quality teams. The ideal candidate has deep expertise in semiconductor packaging technologies and a strong track record of bringing complex products from concept through qualification and high-volume production. Key Responsibilities Lead Advanced Packaging Initiatives: Lead the design, development, and qualification of advanced semiconductor packaging solutions, including: Flip-chip, Chip Embedding Wafer-level packaging (WLP/FOWLP) Panel-level packaging (laminate, molding) 2.5D/3D packaging System-in-package (SiP) Ball grid array (BGA/CSP) Wafer-to-wafer and die-to-wafer heterogeneous bonding Architecture & Simulation: Defin