$ cat jobs/rfic-layout-designer-starshield-silicon-spacex-1b7f0bbad41e.json
RFIC Layout Designer (Starshield Silicon)
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. RFIC LAYOUT DESIGNER (STARSHIELD SILICON) Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As a RFIC Layout Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design, firmware, pre-silicon verification, post-silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical level and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. RESPONSIBILITIES: Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineers to determine pad locations Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout Perform design rule ch