Sr Staff Engineer, Design Verification

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Responsibilities Coding of simulation infrastructure using SystemVerilog (UVM) & C/(ARM,RISC-V Assembly) SoC Level verification is a must. Actively involve in all stages of product development including specification, circuit design, circuit modeling, verification, design for test, and silicon debug. Set up UVM verification environment, develop, and verify self-tested test benches for Mixed Signal chips and sub-circuits. Use and Development of Advanced UVM/mixed-signal simulation techniques to enhance simulation efficiency. Generate Verification Plan from the Specifications using vManager Determine Coverage and design completeness requirements Generate random-constraint tests to cover all customer-use-models Create Assertions, cover-groups, checkers, monitors and automatic reporting Set-