Sr Staff Package Design Engineer

Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, WLCSP, multi-chip module with substrate or embedded die/capacitor and power device packaging. Develop Cu RDL with seed layer on IC wafer and FET and Backside metal deposit after grinding Wafer thinning development through Taiko BG and Glass carrier bond Define substrate, die interconnection through via, materials and PCB interface requirements Package technologies qualification for consumer & industrial power as well as automotive power applications. Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM). Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec. Work with Product groups and Reliability team, qualify new packages and processes within required time frame. Resolve all process integration issues by ensuring all window checks are done on critical process steps. Establish production controls and monitor to ensure there is no room for quality incidents. Ensure smooth transition into production & implement ramp up monitor. Work with OSAT/CM to monitor and resolve process issues early in the production stage to ensure only parts with superior quality shipped to customer. Develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects in LGA. Participate in packaging roadmap development & focus on execution. Address internal and external customer complains working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses. Establish & maintain package design rules Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering. 10-15 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip LGA packaging. Strong understanding of po