$ cat jobs/sr-staff-staff-engineer-rtl-design-renesaselectronics-55c7637e5c79.json
Sr Staff /Staff Engineer, RTL Design
Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Front-End implementation of SERDES high speed Interface PHY/Controller designs RTL development including tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis meeting Automotive coverage targets. Provide support to SoC integration and chip level pre/post-silicon debug. MTech/BTech in EE/CS with hardware engineering experience of 10+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Expe