$ cat jobs/staff-analog-design-engineer-process-migration-verification-d-matrix-1566a99155e5.json
Staff Analog Design Engineer - Process Migration & Verification
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. ROLE OVERVIEW You will lead the migration of proven high-speed SerDes and mixed-signal blocks into new process nodes for d-Matrix's IO chiplet, and own the verification and characterization infrastructure the rest of the analog team depends on. Node migration at these data rates is a design problem rather than a mechanical one — this role exists because we'd rather have someone own it properly than see it absorbed in pieces across the team. This is a hands-on role with clear scope and visible impact on schedule, suited to an engineer who takes satisfaction in making a large body of design work correct, measurable, and reusable. WHAT YOU WILL DO - Own design of existing SerDes and mixed-signal blocks into new process nodes: device mapping, re-sizing, bias/headroom re-budgeting, and re-verification against original specifications. - Identify where a port stops being a port — blocks whose architecture won't survive the node change — and raise those early with a recommendation. - Build and maintain the analog verification infrastructure: testbench frameworks, regression setup, corner and Monte Carlo campaigns, and results management the whole team can rely on. - Run post-layout back-annotated verification and close the loop with layout engineers on parasitic-driven problems. - Generate and maintain behavioral and Verilog-A models of analog blocks for full-chip verification, keeping th
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