Staff Analog Design Engineer, SerDes Clocking

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. ROLE OVERVIEW This is a hands-on, transistor-level analog design role owning the clocking subsystem of d-Matrix's high-speed SerDes on our IO chiplet — including the PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop. This block set most often determines whether a link closes, and you will personally carry your designs from specification through silicon characterization. The work spans porting proven clocking blocks to new process nodes and ground-up design for our next-generation link, partnering closely with datapath, DSP, digital, and firmware teams to close timing, jitter budgets, and calibration across the full SerDes macro. WHAT YOU WILL DO - Own transistor-level design of low-jitter frequency synthesis — LC and/or ring PLL, including loop filter, charge pump or digital loop, VCO, and divider chain. - Own the phase interpolator and phase rotation scheme, including INL/DNL, glitch behavior, and interpolation resolution against the CDR's needs. - Design high-frequency clock distribution across the SerDes macro: buffer chains, duty-cycle correction, quadrature generation and correction, skew control, and supply isolation. - Define and verify CDR architecture and loop dynamics — bandwidth, jitter tolerance, jitter transfer, lock acquisition, and frequency offset tracking — modeling loop behavior in MATLAB, Python, or equivalen