Staff Analog Design Engineer, TX/RX Datapath

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. ROLE OVERVIEW You will own the transmit and receive datapath of the high-speed SerDes on d-Matrix's IO chiplet — the interconnect that lets our inference accelerators scale beyond a single package. This is a hands-on, transistor-level design role on a small team, where you will personally carry blocks from specification through silicon characterization rather than handing specs off to someone else. The work spans porting proven datapath blocks to new process nodes and ground-up design of new blocks for our next-generation link, working closely with layout, package/signal-integrity, backend, and firmware engineers to bring your designs to working silicon. WHAT YOU WILL DO - Own transistor-level design of the SerDes transmit path: output drivers (SST and/or CML), pre-driver and serializer stages, and transmit-side FFE. - Own transistor-level design of the receive front-end: termination and ESD-aware input network, CTLE, VGA, samplers, and where applicable ADC-based front-ends. - Design and verify the equalization path — DFE and FFE architecture, tap resolution, and adaptation behavior — and own the trade study behind the architecture you choose. - Derive block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets, and defend those specifications in design review. - Build the verification environment for your blocks — testbench