ironquill.tech/board

$ cat jobs/staff-analog-engineer-f-m-d-renesaselectronics-3324aa001ff1.json

Staff Analog Engineer (f/m/d)

Renesaselectronics·Worldwide·Edinburgh, GB·senior
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Design and verify CMOS major analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Take technical leadership of full-chip or major system level blocks and drive projects from specification to production ramp. Collaborate with analogue and digital leads to achieve system and design strategy for custom ASICs and drive layout team to high quality physical implementation. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterisation. Work with test and product engineers to support test development and ramp to production. Take a proactive approach to driving own development plan, utilising team members and internal development opportunities. Maintain technical project involvement at principal level and drive consistent methodology engagement across the team. Design and verify analog block-level, sub-system and chip-level circuits to meet the functional and performance specifications of custom mixed-signal ASICs. Lead a group of engineers technically to deliver a given block on time. Translate customer requirements into design specifications and design solutions. Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 8+ years of relevant analog circuit design experience. Hands-on experience in the design and verification of a wide number of analogue circuit blocks such as amplifiers, oscillators, LDOs, comparators, reference/biasing circuits, PMIC and audio sub-blocks Experience in leading the development of switching converter or audio systems. Ability to lead a team and deliver chip level solutions through collaboration with analogue, digital, verification, layout, applications and test teams. Experience of chip-level verification including AMS and DMS. Strong competence with EDA design tools and the Cadence design environment. Enforce common method