Staff Digital Design Engineer

Design optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance. Cover digital backend design from synthesis, upf, static timing analysis and logic equivalent checking. Interface with P&R for digital hand-off and post layout verification. Collaboration with analog engineers and test engineers on analog testability design and debugging. Work closely with Application/GUI team in FPGA prototype and lab debugging. Perform physical silicon device evaluation where necessary. 7+ years of experience in ASIC/IC design with deep knowledge of whole IC design flow from RTL coding, synthesis, static timing analysis, logic equivalent checking to post-layout checking. Experience in DFT or physical design is a plus. Experience in FPGA prototype and lab equipment and lab debug is a plus. Fluent in either Verilog RTL coding and ASIC design methodology. Competence in developing design constraints for synthesis, STA and P&R handoff. Ability to work both independently and part of a team. Excellent interpersonal, organizational and communications skills. Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Elect