Member of Technical Staff, Formal Verification

About the Role We are seeking a Member of Technical Staff, Senior Formal Verification Engineer. In this role, you will be responsible for developing and executing formal verification strategies and techniques to ensure design correctness. You will collaborate closely with Architects, RTL Design and Verification Engineers to understand the requirements, develop formal verification infrastructure and drive closure on the critical design blocks. You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration. The ideal candidate possesses strong expertise in formal verification methodologies, SystemVerilog assertions (SVA), RTL design concepts and industry standard formal verification tools. This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA. Essential Duties & Responsibilities - Analyze architecture and design specifications to identify the formal verification requirements. - Develop and execute formal verification plans for Netpreme silicon, IP and subsystems. - Build formal verification environments, SystemVerilog Assertions (SVA), formal properties including assumptions, constraints, abstractions and checkers. - Perform property checking, model checking, equivalence checking, deadlock and livelock analysis. - Debug formal verification failures, analyze counter examples and work with design team to resolve issues. - Drive verification closure through formal coverage analysis and proof convergence. - Contribute to verification methodology improvements and formal verification best practices. - Mentor junior verification engineers and provide technical leadership within the team. - Participate in design reviews, architecture discussions, verification reviews and sign-off activities. - Collaborate with Simulation, Emulation and validation teams to ensure comprehen